Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.
Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.
Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s 32/28-nm process technology.
Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.