Tag Archives: Design Flow

Arteris and EVE Design Flow for System-on-Chip Development

Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.

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AWR Connected for ODB++

AWR Connected for ODB++ is a PCB layout verification design flow for connecting third party PCB tools and AWR software (Microwave Office RF/microwave circuit simulation and AXIEM electromagnetic analysis software). It enables the flow of PCB layout data (exported from vendor tools in ODB++ format) into AWR’s Microwave Office / AXIEM software for post-layout, final design-stage verification. The ODB++ PCB flow moves layout data from an engineer’s PCB vendor tool into a relevant and independent file format ready for use and import into AWR software. AWR Connected for ODB++ is available now.

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Cadence Digital End-to-end Flow for 28nm Giga-gate/Gigahertz Designs

Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire chip flow holistically. It supports Cadence’s approach to Silicon Realization, which is a key element of the EDA360 vision. The new flow is available now.

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RTL-to-GDSII Silicon Realization Reference Flow for Common Platform

Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.

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Magma Reference Flow for Common Platform 32/28nm Low-Power Process

Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s 32/28-nm process technology.

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Mentor Graphics and Dongbu HiTek Technology Design Kits for Analog BCDMOS

Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.

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Magma, Virage Logic Reference Flow for GLOBAL FOUNDRIES 65nm Process

Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.

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Extreme DA GoldTime for Altos Variety and Liberate Models

Altos Design Automation and Extreme DA developed a signal-integrity (SI) design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below. Extreme DA GoldTime for use with Altos Variety and Liberate models is available now from Extreme DA. Pricing varies depending on configuration. Altos Variety and Liberate approved libraries for Extreme DA GoldTime are available now from Altos.

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SMIC-Cadence 65nm Low Power Reference Flow 4.0

Cadence Design Systems introduced a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation (SMIC). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform. The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability.

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