Synopsys introduced a comprehensive design implementation solution for TSMC’s 16-nanometer (nm) FinFET reference flow. The jointly developed reference flow is built on tool certification currently in TSMC’s V0.5 Design Rule Manual (DRM) and SPICE. The collaboration between the two companies has resulted in a comprehensive FinFET implementation flow that can be deployed for production use by mutual customers.
Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.
Synopsys’ unified mixed-signal IC design solution has been qualified for TowerJazz’s power management analog/mixed-signal reference design flow (Reference Flow 2.0) and 180-nanometer (nm) Power Management (PM) interoperable process design kit (iPDK). Synopsys’ tool suite, the foundry iPDK and reference design flow are verified to seamlessly work together to enable designers to quickly become productive.
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.
element14 is hosting a webinar tomorrow. The webcast will present a step-by-step guide to debugging an ARM based design with the Keil ULINK-ME debug adapter. Attendees of the webcast will also be invited to apply to RoadTest the Keil ULINK-ME, bundled with an ARM Cortex-M processor-based STM32 series development kit. element14′s RoadTest Group enables developers to test and review new products, and post their results and findings on the element14 Community. The online seminar is a part of their Design Flow Series webinar series. The free event will take place on June 19, 2012, at 10 am EST (16:00 CET).
Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.
element14 is hosting a series of design flow webinars. The first webcast is about programming the Raspberry Pi. It features Raspberry Pi co-founder Eben Upton. The first online seminar will take place on April 4th at 10am EST (2pm GMT, 3pm BST). The Design Flow webinar series offer hints and tips, as well as useful techniques that help drive the design flow.
Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.
Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.
Cadence Design Systems and ClioSoft is offering a webinar about the major new enhancements in Virtuoso IC 6.1.5. The webcast will explain how parasitic-aware design and HCM techniques can help accelerate time to market. The event is titled, Cadence Virtuoso (IC 6.1.5) Technologies, Parasitic-aware Design Flow and Design Management. The one-hour online seminar will take place Thursday, April 14th, 2011 at 11:00 am Pacific time. The webcast is ideal for CAD engineers/managers and analog, mixed-signal, custom IC design and layout engineers/managers.