Tag Archives: Real Intent

Real Intent Releases New Version of Ascent X-Verification System Tool

Real Intent Ascent X-Verification System (XV) tool

Real Intent introduced the latest version of Ascent X-Verification System (XV) tool for early functional analysis of digital designs. The new version features enhancements for initialization analysis, and the detection and management of unknown logic values (X’s). The latest version of Ascent XV is available now for download.

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Real Intent Launches Meridian CDC 5.0 Analysis Tool

Real Intent launched version five of their Meridian CDC tool. The new hierarchical CDC flow supports partitioned analysis of designs without sacrificing top-level full-chip precision for giga-scale sign-off. Meridian CDC’s hierarchical flow avoids the compromises found with abstract-modeling and the use of waivers in other products. Meridian CDC v5.0 will be available July 1, 2013. Pricing depends on product configuration.

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Real Intent Updates Ascent Implied Intent Verification, X-Verification

Real Intent Ascent Implied Intent Verification (IIV)

Real Intent launched the latest version of Ascent Implied Intent Verification (IIV) and Ascent X-Verification (XV) tools. Ascent IIV and Ascent XV offer enhanced support for SystemVerilog, Verilog and VHDL languages, and improve ease of use in both the GUI and low-noise reporting of design issues. The tools also include Verdi3 integration. The newest releases of Ascent IIV and Ascent XV are available now for download. The EDA tools are ideal for early functional analysis of digital designs.

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Real Intent Introduces New Version of Meridian Constraints

Real Intent Meridian Constraints

Real Intent introduced the latest version of their Meridian Constraints product for comprehensive design constraint management. This new software release features enhanced speed, analysis and SystemVerilog language support. The new release of Meridian Constraints is available now. Pricing depends on product configuration.

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Real Intent Releases Meridian Clock Domain Crossing v4.0

Real Intent rolled out version four of their Meridian Clock Domain Crossing (CDC) verification software. The CDC verification tool can be used to achieve complete CDC sign-off for large and complex SoC designs from RTL to gate. The latest version includes improvements that make it the only software solution that enables complete CDC sign-off for over 100M gate SoC designs. Meridian CDC v4.0 is available now.

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Real Intent Ascent Lint 1.4

Real Intent released version 1.4 of Ascent Lint solution for performing syntax and semantic lint checks for complex SoC designs. Ascent Lint 1.4 includes new features to improve design productivity and the comprehensiveness of rule checking. These features incremental reporting, scope-based analysis, and enhanced waiver capabilities. Real Intent Ascent Lint 1.4 is available now.

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Real Intent Meridian DFT

Real Intent announced Meridian DFT for improving electronic design quality. Meridian DFT indentifies trouble spots during RTL creation. Meridian DFT checks the pre- and post-synthesis RTL for testability and DFT-related implementation errors. Meridian DFT will be available in Q3 2010.

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Real Intent Ascent Lint v1.3

Real Intent rolled out version 1.3 of Ascent Lint. The new version adds VHDL checks to its existing Verilog checks. It is a tool that performs syntax and semantic Hardware Description Language (HDL) lint checks for complex SoC designs. Ascent Lint features a fast engine and low noise report for debugging electronic designs. Ascent Lint 1.3 is available now.

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Real Intent Meridian Clock Domain Crossing Verification Software 3.0

Real Intent released Version 3.0 of Meridian Clock Domain Crossing (CDC) verification software. Meridian CDC is a precise and comprehensive CDC solution. It uses a multi-strategy analysis approach that includes Automatic Clock Intent Analysis, Formal Analysis, Hierarchical Analysis, and Dynamic Analysis (SimPortal). Meridian CDC 3.0 is available now.

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Real Intent Ascent Lint v1.2

Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.

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