Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock speed, up to 20% smaller die area and up to 15% less power consumption. The Diamond Standard processors are available now.
Mentor Graphics introduced the Mentor Embedded Inflexion User Interface (UI) for rapid customization and differentiation of Android-based devices built using the Zoom OMAP36x-III mobile development platform (MDP). The Zoom OMAP36x-III MDP features the Texas Instruments (TI) OMAP3630 processor. The Inflexion UI is available on Android. It is ideal the Zoom OMAP36x-III MDP and TI’s OMAP processor-based eBook development platform.
Macraigor Systems’ On-Chip Debug Technology (OCDemon) now supports the Intel Atom x86 processor. Macraigor’s JTAG interface devices are immediately available for use with the Intel Atom based designs as well as other Intel family devices including the XScale family of processors. OCDemon for the Intel Atom is available immediately starting at $250 USD. The port of the GNU Tools Suite and Eclipse Ganymede/Galileo platform is being offered at no charge.
The LPCXpresso, from NXP Semiconductors, is a development tool platform for the LPC ARM processor family of microcontrollers. The LPCXpresso features an easy-to-use interface and supports the complete product design cycle, providing an end-to-end development solution. LPCXpresso is designed for the beginner as well as the advanced designer. LPCXpresso users can now evaluate, explore and develop within a single easy-to-use interface while retaining all the advanced features associated with powerful and expensive tools. The LPCXpresso tool platform is available now for $29.95 (US).
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.
Coware is offering a webinar, entitled “Custom Processor / Programmable Accelerator Design and Implementation.” The webcast will take place Wednesday, November 11, 2009 at 10:00 am Pacific (1:00 pm Eastern). The online seminar is one hour long and is free to attendees. The webinar will be presented by Drew Taussig (Senior Product Specialist for the Processor Design solutions at CoWare).
Open-Silicon, MIPS Technologies, and Virage Logic teamed to develop test chips showcasing the companies’ technologies for building high-performance processor-based systems. The companies achieved successful 65 nanometer (nm) silicon testing of a processor test chip at 1.1GHz, making it one of the fastest processors built in a 65nm ASIC. In addition, the companies are now working on a follow-on 40nm device targeting frequencies in excess of 2.5GHz and providing over 5000 DMIPS of performance. Both efforts utilize Open-Silicon’s CoreMAX technology as well as the superscalar MIPS32 74K processor core, a fully synthesizable processor core widely used in high-end digital consumer devices, set top boxes, and networking solutions.
The ARM Cortex-A5 MPCore processor is a small, lowest power ARM multicore processor capable of delivering the Internet. The Cortex-A5 processor is available as an extremely area- and power-efficient uniprocessor or up to a 4x multicore processor. The processor is ideal for ultra low cost handsets, feature phones, smart mobile devices, pervasive embedded devices, consumer devices, and industrial devices. The Cortex-A5 processor is now available for general licensing and will be delivered in the fourth quarter of 2009.
Synopsys has created an optimized reference implementation methodology for the ARM Cortex-A8 processor that achieves greater than 2GHz (4000 DMIPS) at 540mW. The result was accomplished by combining optimized methodology, tools, and ARM Physical IP to enable new classes of mobile and tethered devices requiring the combination of high-performance and energy efficiency. The Synopsys Galaxy Implementation Platform methodology (scripts and documentation) for the 2GHz ARM Cortex-A8 optimized implementation is available from ARM and Synopsys.
Version 5.40 of IAR Embedded Workbench now supports ARM supports ARM Cortex-R4(F) processor. IAR Embedded Workbench is a set of development tools for embedded applications. The package includes an editor, project management tools, a C and C++ compiler that generates highly optimized code for the combined ARM/Thumb-2 instruction set, a C-SPY simulator as well as run-time libraries, relocating assembler, linker and librarian tools. The compiler can check against the rules of MISRA C (MISRA C:2004) software development standard as established by the Motor Industry Software Reliability Association.
More info: IAR Systems