Tag Archives: Process

Cadence Encounter Digital Platform Optimizes ARM POP IP

ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.

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Synopsys DesignWare IP Available for SMIC 40-nanometer Low-Leakage Process

Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

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SMIC-Synopsys Reference Flow 5.0 Extends 40nm Low Power Capabilities

SMIC-Synopsys Reference Flow 5.0

Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.

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Magma Reference Flow for Common Platform 32/28nm Low-Power Process

Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s 32/28-nm process technology.

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X-FAB Sense, Process, Actuate Technical Seminar

X-FAB Silicon Foundries is offering a free technical seminar: Sense, Process, Actuate. The lunch and learn event will take place on October 12th (Irvine, CA) and 14th (Santa Clara, CA) from 10 am to 2 pm PST. The four-hour seminar is ideal for engineers seeking support for the design and manufacture of System-on-Chip (SoC) solutions for CMOS / MEMS integration, analog mixed-signal and power management applications.

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Magma, Virage Logic Reference Flow for GLOBAL FOUNDRIES 65nm Process

Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.

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X-FAB XO035 Process for Blu-ray and Optical Data Communication

X-FAB Silicon Foundries announced the XO035 0.35 micrometer process. The XO035 foundry process is optimized for Blu-ray and high-speed optical data communication applications. XO035 includes X-FAB’s blue PIN module. The integration of the PIN diode into the 0.35 micrometer CMOS environment enables the design of high-performance photo detectors. The XO035 process is available now.

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CEVA Embedded Processors Webinar

CEVA will host a webinar on January 12, 2010 at 8:00 am Pacific (11:00 am Eastern / 16:00 GMT). The title of the webcast is: Optimize your Software Development Flow — An intelligent C-level development process for modern embedded processors. Overview: In the online seminar, CEVA will explore the latest challenges in software development for advanced embedded architectures and propose a practical flow to meet target performance with minimal risk and shortest development time.

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Process Design Kits for UMS PH15 and PH25 GaAs MMIC Foundry Processes

AWR and United Monolithic Semiconductors (UMS) introduced enhanced process design kits (PDKs) for the UMS PH15 and PH25 advanced gallium arsenide (GaAs) foundry processes. The enhanced PDKs enable designers to take full advantage of the process capabilities of UMS within AWR’s 2009 Microwave Office design suite including its latest technologies such as iNets, AC0E, AXIEM, and ICED DRC. Engineers can also take advantage of the fact that the PDKs are now release-independent from AWR’s own software upgrade cycle. PDKs from UMS are available to active customers of the UMS foundry and AWR software.

More info: AWR

SEMATECH to Reveal Device and Process Breakthroughs at IEDM

At the IEEE International Electron Devices Meeting (IEDM), engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs. SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage — a significant process technology advancement for next-generation logic and memory technologies. The IEDM Conference will take place December 7-9, 2009, at the Hilton in Baltimore, MD.

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