ANSYS introduced RTL Power Model (RPM). Their technology helps engineers optimize a wide range of power-sensitive applications. It bridges the power gap from register transfer language (RTL) design to physical implementation. RPM accurately predicts integrated circuit (IC) power behavior at the RTL level with consideration for how the design is physically implemented. RTL Power Model enables chip power delivery network (PDN) and IC package design decisions early in the design process.
Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.