Tag Archives: Pin-level

Pin-level SystemC Models of Xtensa Customizable Dataplane Processors

Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.

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