Tag Archives: Physical Verification

Synopsys Galaxy Implementation Platform Supports TSMC 20nm Process

Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.

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Synopsys IC Compiler-Advanced Geometry for 20nm IC Implementation

Synopsys introduced IC Compiler-Advanced Geometry, which is a new configuration of their IC Compiler physical design product. IC Compiler-Advanced Geometry is a DPT-compliant place-and-route solution that will provide designers moving to 20 nanometers with an advanced solution. Synopsys has successfully collaborated with foundry partners and major customers to validate that IC Compiler is 20nm-ready.

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POLYTEDA One-Shot DRC Processing and Fine-Grain Physical Verification

POLYTEDA Software introduced One-Shot DRC processing and Fine-Grain Physical Verification (fgPV) for dealing with design densities and process complexities of nanoscale deep sub-wavelength process technologies. One-Shot DRC processing is different from hierarchical and traditional flat DRC processing. One-Shot takes all layers, and all rules associated with those layers, and processes them in one shot. For a given number of objects in a design, the architecture of One-Shot DRC is unique in producing predictable and almost linear runtime performance.

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