Cadence Design Systems introduced a new SpeedBridge Adapter for PCIe 3.0. The adapter provides easy bring-up and fast debug of PCIe-based designs when used with a Cadence Palladium Verification Computing Platform, and is backwards compatible with PCIe 2.0-, 1.1- and 1.0a-based designs. The Cadence SpeedBridge Adapter for PCIe 3.0 is available now.
Cadence Design Systems recently introduced their PCIe Controller and PHY solution. The new design IP is ideal for low-power PCI Express (PCIe) development. The PCIe 3.0 controllers and PHY will help designers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts. The solution is ideal for datacenter and enterprise applications.
Cadence Design Systems has added new capabilities in their PCI Express Verification IP. The Cadence PCIe VIP now offers more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct advantages for PCI Express verification. Cadence’s VIP solution includes over 40 interface protocols and more than 6,000 memory models that have been deployed in thousands of designs.
The PCI Express Base 3.0 specification is now available to PCI-SIG members. The PCI Express Base 3.0 specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. PCIe 3.0 technology maintains backward compatibility with previous PCIe architectures and is ideal for high-volume platform I/O implementations across a wide range of topologies (servers, workstations, desktop and mobile personal computers, embedded systems, peripheral devices, etc).
LeCroy introduced SimPASS PE simulation design verification tool for PCI Express 3.0 protocol testing. LeCroy’s SimPASS PE provides designers with a new way to observe and analyze PCI Express-based I/O traffic. SimPASS is ideal for the pre-silicon simulation and design verification phases of development. SimPASS is based on the existing LeCroy graphical user interface for display and analysis of data traffic, and extends the data traffic analysis capabilities commonly used for post silicon testing to the simulation environment. SimPASS for PCI Express is now available.
SystemVerilog-based and Open Verification Methodology (OVM)-compliant PCI Express Gen3 verification IP (Genie-PCIe3 VIP) is now available from Perfectus Technology. Genie-PCIe3 VIP helps designers accelerate the verification of PCI Express Gen3-based products. Genie-PCIe3 features a complete set of intelligent verification components for verifying PCI Express 1.1/2.0/3.0 and SR-IOV-based designs and it works in any verification environment, including SystemVerilog and OVM methodology. PCIe Gen3 VIP is available immediately.
ASSET’s ScanWorks platform for embedded instrumentation now supports the PLX visionPAK packet generator/system analyzer toolset. visionPAK provides unique capabilities embedded in PLX PCIe devices helping engineers with board level testing and field debug. ASSET ScanWorks support will enable system manufacturers to use PLX on-board devices to test other components and interconnects of the system more rigorously with lower cost before they get shipped.