The Design and Verification Conference (DVCon) has issued a call for paper and panel abstract submissions, and tutorial proposals. DVCon wants engineers to present their experiences, solutions and ideas. Paper proposals are due August 15, 2011, tutorial proposals are due September 13th, and panel proposals are due September 19th. DVCon will be held February 27-March 1 in San Jose, California. DVCon 2012 is sponsored by Accellera.
Synopsys will host an online synposium from August 31st to September 2nd. The virtual event will feature Synopsys’ EDA software, IP, prototyping, and services for semiconductor design, verification and manufacturing. During the event, engineers can chat with Synopsys technical staff and view product demos, webinars, and technical papers. Designers can view synposium materials on-demand through December 3, 2010.
Satin IP Technologies will be in a panel at the IP-Embedded Systems Conference in Grenoble, France on December 1, 2009 from 17:15 to 18:45. They will discuss improving intellectual property (IP) quality without losing design productivity. The panel (entitled Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?) will discuss issues that arise when time-to-market and cost reductions dominate IP design and integration, since instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers.