Cadence Design Systems announced version 16.5 of their Allegro PCB and IC packaging technology. Allegro v16.5 features advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, improved co-design, and flexible team-design enablement. The new features and capabilities improve the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization. Cadence Allegro 16.5 will be available in late May. Allegro 16.5 technology will also be available through product configuration with on-demand features for specific design tasks.
Apache Design Solutions announced a workshop at DesignCon 2010 to facilitate industry-wide discussion on the challenges, methodologies, and techniques required for chip-package-systems (CPS) convergence. The workshop, entitled “Practical Methodologies for Power/Signal Integrity of Chip-Package-Board Designs,” will be held from 9am to noon on Thursday, February 4th in the Santa Clara Convention Center.