ProPlus Design Solutions launched NanoYield design for yield software. It is a fast and accurate yield prediction and optimization tool for memory, logic, analog and digital circuit design. The toolset is faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis. NanoYield is part of ProPlus Design Solutions’ transistor-level statistical modeling and design and variations-aware product portfolio. It is shipping now.
Carbon Design Systems is accelerating the analysis, optimization and verification of system-on-chip (SoC) performance with their new Carbon Performance Analysis Kits (CPAK). The CPAK family for ARM Cortex processors includes reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE subsystem. The CPAK Family for ARM Cortex A-Series Processors will be available in bare metal and Linux configurations in this quarter. Android configurations will be available in the second half of this year.
AgO introduced AnXplorer 2010.12. The latest release features new feasibility analysis capability for rapidly identifying a feasible region for circuit design variables. AnXplorer 2010.12 increases productivity for analog IC designers. AnXplorer is a circuit optimization tool for analog and RF design. It uses an optimization approach that is based on either simulation or equations. The tool works with SPICE netlists and supports industry standard simulators — including Synopsys HSPICE, Cadence Spectre, Mentor Eldo and Legend Design Technology MSIM. AnXplorer runs on the Linux operating system.
AgO introduced AnXplorer, which is a circuit optimization tool for analog and RF design. Its optimization is based on either simulation or equations. The tool works with industry standard SPICE netlists and supports industry standard simulators including Synopsys HSPICE, Cadence Spectre and Legend Design Technology MSIM. It runs on the Linux operating system. Starting with an unsized SPICE netlist, variables for device dimensions and a set of design objectives and constraints, AnXplorer optimizes device sizes by exploring the design space.
CEVA launched the Application Optimizer, which is an integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox Software Development Environment, the Application Optimizer enables application developers to easily develop software for CEVA’s DSPs purely in C-Level, eliminating any hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs.