Mentor Graphics has extended their Universal Verification Methodology Connect tool for the Open Verification Methodology (OVM) community. UVM Connect 2.2 can now be compiled to run with the OVM. The UVM Connect architecture facilitates easy connection with other environments beyond the initially supported UVM and SystemC. With the updated UVM Connect, teams using OVM can connect with SystemC models and other environments.
Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.
Denali Software has an archived webinar about verification: Advanced Verification with OVM and PureSpec. The on-demand webcast explains how to maximize productivity in an Open Verification Methodology (OVM) environment. The webinar will highlight various OVM and PureSpec features and give examples of how to implement these various attributes into a full-scale verification environment.
SystemVerilog-based and Open Verification Methodology (OVM)-compliant PCI Express Gen3 verification IP (Genie-PCIe3 VIP) is now available from Perfectus Technology. Genie-PCIe3 VIP helps designers accelerate the verification of PCI Express Gen3-based products. Genie-PCIe3 features a complete set of intelligent verification components for verifying PCI Express 1.1/2.0/3.0 and SR-IOV-based designs and it works in any verification environment, including SystemVerilog and OVM methodology. PCIe Gen3 VIP is available immediately.