Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.
Artisan Software Tools has acquired Extessy, which is a supplier of development tools and services for system requirements, co-simulation, integration, and test. Extessy’s tools and services complement Artisan’s existing model-based solutions for mission, safety, and life-critical complex systems development. They add important capabilities in terms of system requirements interchange and management, co-simulation and test automation.
The Open Virtual Platforms (OVP) initiative has released new models of ARM processor cores. The new models work with the OVP simulator, OVPsim, and can perform at hundreds of millions of instructions per second (MIPS). The ARM models released are for the v4 and v5 instruction sets from ARM, supporting 13 processor cores across the ARM7, ARM9 and ARM10 families of processor cores. This includes the ARM926E processor core, the most popular core developed by ARM. In addition to making the models for ARM processors available as free and open source, OVP offers free, open source example virtual platforms for OVP users.