SinelaboreRT is a tool for real-time embedded systems developers. SinelaboreRT generates readable and maintainable code from UML modeling tools. The generated code does not require a runtime library and can be easily used in different system designs (RTOS, foreground-background) or even in an IRQ handler. With SinelaboreRT, engineers can convert state-machine models into a target language (C++, Java and C#). Designers can influence the generation process according to thier needs. The built in state-chart editor supports model state diagrams without using a UML tool.
Altos Design Automation and Extreme DA developed a signal-integrity (SI) design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below. Extreme DA GoldTime for use with Altos Variety and Liberate models is available now from Extreme DA. Pricing varies depending on configuration. Altos Variety and Liberate approved libraries for Extreme DA GoldTime are available now from Altos.
Magma Design Automation introduced SiliconSmart ACE Memory Characterization. It features the FineSim Pro simulation technology, dynamic circuit reduction through smart netlist pruning, automatic internal node identification, constraint acceleration, and template-guided function descriptions for vector generation. With SiliconSmart ACE Memory Characterization, integrated circuit (IC) designers can reduce turnaround time and deliver better results for designs targeted at 28-nanometer (nm) and smaller process nodes. SiliconSmart ACE Memory Characterization is an extension to SiliconSmart ACE and is available now.
AWR Corporation published a new white paper, entitled X-parameters and Beyond, AWR’s Support of PHD and Nonlinear Behavioral Models. The white paper provides comprehensive information about rapidly-emerging nonlinear models and measurement systems and how AWR’s Microwave Office high-frequency design software effectively employs them.
Geensoft introduced the AUTOSAR Re-targeting Tool (ART) module for the AUTOSAR Builder tool suite for the development of AUTOSAR-compliant automotive embedded systems. The ART module offers automatic generation of AUTOSAR-compliant C code that is ready to be embedded on target ECUs, from both new and legacy MATLAB/Simulink models using RTW.
Carbon Design Systems unveiled virtual models for ARM Mali Graphic Processor Units (GPUs). The new Mali models represent the first in a new generation of ARM models from Carbon Design Systems. The built-in TLM-2.0 interface gives each model the flexibility for architectural exploration, firmware development and application software development. Mali models are available now from Carbon Design Systems.
The Open Virtual Platforms (OVP) initiative released a reference virtual platform of the ARM Integrator development board using OSCI SystemC TLM-2.0 C++. The virtual platform includes all the models needed for the virtual platform to enable users to run Linux. The virtual platform can be executed either in the OVP simulator (OVPsim), or in a SystemC/TLM-2.0 simulation environment using any of the industry SystemC/TLM-2.0 simulators. The virtual platform and all models are free and available as open source.
CoFluent Design has developed a new methodology that combines the OMG’s (Object Management Group) standards UML (Unified Modeling Language), SysML (System Modeling Language), and MARTE (Modeling and Analysis for Real-Time and Embedded Systems) profile. By offering a link from UML to CoFluent Studio and its automatic SystemC code generation, CoFluent Design makes UML models executable and applicable for multicore system virtualization and performance prediction.
Carbon Design Systems and VeriSilicon have integrated VeriSilicon’s ZSP models into the Carbon SoC Designer virtual platform. VeriSilicon processors enable users to perform implementation-accurate architectural analysis and pre-silicon firmware development. The VeriSilicon ZSP integration is available now from Carbon Design Systems.
CoFluent Studio can now be used for the creation and automatic generation of SystemC models and test cases for the Mentor Graphics Questa functional verification platform. The automatic SystemC transaction-level modeling (TLM) code generation allows reuse of IC and use case models for validating the register-transfer level (RTL) implementation in Questa.