EMA Design Automation (EMA) and AEi Systems have announced the latest version, 4.1, of the AEi Systems’ Power IC Model Library for the Cadence PSpice simulator. “This update to the power IC model library will make it easier for our PSpice customers to obtain high quality bench tested models,” says Manny Marcano, President and CEO of EMA.
Cadence Design Systems released new verification IP (VIP) models for the latest memory standards: LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM. LPDDR4 and Wide I/O 2 are key new standards for memory interfaces, and the availability of memory models will help designers to take advantage of the new standards quickly.
Carbon Design Systems recently released the latest version of SoCDesigner Plus. The new version expands the models eligible to be used with Swap & Play. SoCDesigner Plus automatically supports all fabric and DDRx memory controller components. As a result, many more design teams can boot an operating system in seconds and then debug with 100% accuracy using Swap & Play. Carbon’s newly enhanced Swap & Play support and updated CPAKs are available now for all SoCDesigner Plus users.
Mentor Graphics has made improvements to the Verification Academy. One of the new enhancements in the Verification Academy is the Coverage Cookbook. The Coverage Cookbook is a systematic methodology for developing functional coverage models and coverage-driven processes. The Mentor Verification Academy is a comprehensive resource for verification engineers, and provides access to information and online training on advanced functional verification technologies.
Mentor Graphics introduced a new Flowmaster tool for system level thermo-fluid simulation. The Flowmaster Power and Energy software tool features a two-phase solution that models the phase change from liquid to vapor for steam generation or from vapor to liquid when steam is consumed. The new Flowmaster tool will be available this summer and will support Windows 7 64-bit and Enterprise deployment. The product is ideal for the power generation applications.
Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.
Synopsys recently worked with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). The collaboration has resulted in a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing.
SynaptiCAD rolled out a new verion of TestBencher Pro, which is a VHDL and Verilog system-level testbench generation software. The tool simplifies the process of creating and applying random bus transactions to RTL and gate-level models. The latest version of TestBencher Pro simplifies the creation of testbenches that reside in a different compiled library from the design being tested.
Carbon Design Systems announced a TLM-2.0 solution for the AMBA protocol. The solution enables modeling the AMBA protocols with SystemC TLM2-0. The TLM-2.0 for the AMBA protocol solution will execute in any SystemC environment and contains no runtime licensing. Engineers can create models representing AMBA intellectual property (IP) blocks at any level of abstraction. The TLM-2.0 for the AMBA protocol solution is available for free from Carbon’s IP Exchange.
Atego rolled out Artisan Studio ParaSolver, which is an add-on module for Artisan Studio standards-based, model-driven development tool suite. Artisan Studio ParaSolver increases the design power of Artisan Studio by providing embedded system engineers with the ability to secure their design decisions. Artisan Studio ParaSolver increases design quality assurance and reduces overall design time and costs by providing system engineers with the ability to easily identify the best design compromises and enabling optimal design solutions to be quickly determined.