Cadence Design Systems introduced Virtuoso Advanced Node, which is a set of custom/analog capabilities designed for the advanced technology nodes of 20 nanometers and below. Virtuoso Advanced Node enables design teams to optimize designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.
Cadence Design Systems announced a new publication: Mixed-Signal Methodology Guide. The design methodology book provides an overview of the design, verification and implementation methodologies required for advanced mixed-signal designs. The book addresses the complex problems facing the mixed-signal design community. It features mixed-signal design experts from Boeing, Cadence, ClioSoft and Qualcomm. The Mixed-Signal Methodology Guide is intended for chip designers and CAD engineers.
ASSET InterTech announced Component Action, which is a new model-based test methodology for the ScanWorks platform for embedded instruments. ScanWorks Component Action extends non-intrusive boundary-scan (JTAG) test coverage to devices that previously could not be tested or programmed with boundary scan. The Component Action models will be available in November as a capability of the ScanWorks platform. Pricing for ScanWorks starts at $5,995.
Aldec introduced ALINT 2010.06, which is a design rule checking software solution. ALINT 2010.06 features a phase-based linting (PBL) methodology that provides structured and prioritized phases for the analysis of HDL design issues. The design rule checking tool reduces the number of linting iterations and error messages at each phase. ALINT eliminates more design issues incrementally at each phase. Default phases may be modified or customized by engineers for adherence to corporate design policies or conducting targeted design rule checks. The latest release of ALINT is available now. The tool supports STARC, RMM, DO-254 and Aldec design rule plug-ins, which are sold separately.