Tag Archives: memory

Cadence Design Systems Seeks Papers for MemCon 2013

Cadence Design Systems has issued a call for papers to be presented at MemCon 2013. Cadence is seeking presentations and papers on topics that illustrate users’ knowledge and expertise in memory design and architecture. The deadline for paper abstract submission is May 30, 2013. The MemCon conference showcases the thought leaders driving advances in memory technology. The event will take place August 6, 2013 at the Santa Clara Convention Center.

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Microchip Technology Introduces Parallel SuperFlash Development Kit

Microchip Technology Parallel SuperFlash Kit 1

Microchip Technology introduced the Parallel SuperFlash Kit 1. The development kit features two Parallel Flash PICtail Plus daughter boards, one with a 64 Mbit device (the SST38VF6401) from the Advanced MPF+ family, and one with a 16 Mbit device (the SST39VF1601C) from the MPF+ family. The Parallel SuperFlash Kit 1 (part #AC243006-1 is available now for $30.

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ProPlus Design Solutions Debuts NanoYield Design for Yield Software

ProPlus Design Solutions launched NanoYield design for yield software. It is a fast and accurate yield prediction and optimization tool for memory, logic, analog and digital circuit design. The toolset is faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis. NanoYield is part of ProPlus Design Solutions’ transistor-level statistical modeling and design and variations-aware product portfolio. It is shipping now.

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Magma Design Automation Silicon One Initiative

Magma Design Automation announced their Silicon One initiative. Silicon One features differentiated solutions and technologies for improving time to market, product differentiation, cost, power and performance. The goal of the initiative is to make silicon profitable for chip makers. The Silicon One initiative currently focuses on five types of devices: ASIC/ASSP, Analog/Mixed-Signal, Memory, Processing Cores, and System-on-Chip.

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Synopsys Enhanced DesignWare Universal DDR Memory Controller

Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.

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White Paper: Memory Subsystem Model for Evaluating Network-on-Chip Performance

Open Core Protocol International Partnership (OCP-IP) published a white paper titled “A Memory Subsystem Model for Evaluating Network-on-Chip Performance.” The technical paper discusses performance characteristics of DRAM memories that affect NoC evaluation. Work on the white paper was completed by the OCP-IP Network on Chip Benchmarking Working Group led by Tampere University of Technology and Sonics Inc.

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Synopsys DesignWare STAR ECC IP

Synopsys’ DesignWare STAR Memory System product family now features Self-Test and Repair Error Correcting Codes. The DesignWare STAR ECC IP is a configurable IP solution that enables designers to achieve a higher level of protection against transient errors compared to the classic ECC approach and deliver a more reliable product to the market. The DesignWare STAR ECC IP is designed to provide optimal performance of partial word writes and improved error detection/correction capability in multi-bit upsets and random bit errors.

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Imec Develops Narrow Pitch Interconnects

Imec created the first electrically functional copper lines embedded into silicon oxide using a spacer-defined double patterning approach. According to imec, this is a major step towards 20nm half pitch interconnects. Spacer-defined (or self-aligned) double patterning has recently gained interest as the patterning technique for future FLASH memory devices. Memory vendors will benefit from this research.

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e-MMC based Embedded Memory Architectures Webinar

Toshiba America Electronic Components (TAEC) and Denali Software are offering a webinar titled, eMMC-based Memory Architectures: Trends, Design Considerations and Trade-offs. The webcast will review the new features of eMMC v4.4, and discuss how it can be integrated into mobile phones or other CE device in multiple ways such as a discrete eMMC device, a DRAM+SLC+eMMC multi chip package (MCP), DRAM + eMMC MCP or a package on package (POP) stacked device.

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Memristors Capable of Logic Functions

HP Labs researchers have discovered that the memristor is capable of performing logic functions. As a result, it may be possible in the future to have computations performed in chips where data is stored instead of on a specialized central processing unit. A memristor is a resistor with memory that represents the fourth basic circuit element in electrical engineering.

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