Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.
Variety MX, from Altos Design Automation, is a fast and accurate statistical timing model generator for embedded memories. Variety MX generates instance-specific Liberty models for use by Cadence’s Encounter Timing System GXL, Extreme DA’s Goldtimetm, and Synopsys PrimeTime VX. Variety MX is able to characterize memory sizes that cannot be adequately simulated using brute Monte Carlo methods or even with fast sampling techniques. Variety MX is available now.