SpringSoft introduced the Laker Blitz chip-level layout editor. The new software tool is optimized for speed and productivity during the final steps of the physical design process. It streamlines tapeout-to-manufacturing operations by enabling high-speed viewing and editing of chip-level layouts. Laker Blitz is ideal for designs with large data sets, such as advanced-node system-on-chip (SoC) implementations and large memory chips that are widely used in consumer electronics. The new SpringSoft software is available now for production use.
Mentor Graphics introduced their Valor MSS Business Intelligence (BI) PCB design-through-manufacturing product suite. The Mentor Valor MSS BI features reports and analysis of the quality, asset utilization and materials management of their production execution. The Business Intelligence tool helps engineer managers to make intelligence-based decisions, improve production line execution, and reduce excess inventories. The Valor MSS Business Intelligence (BI) product suite is available now as an option if the Valor MSS suite of manufacturing execution support products.
International SEMATECH Manufacturing Initiative (ISMI) announced the Total Equivalent Energy Calculator II (TEECalc II). The web-based software tracks and evaluates the energy performance of semiconductor manufacturing equipment in order to reduce energy consumption and improve energy efficiency. TEECalc II helps IC and equipment manufacturers identify areas to make critical energy performance improvements to their process equipment and facilities. TEECalc II capabilities have been expanded and improved from TEECalc I. The TEECalc II is available now.
Mentor Graphics is offering a webinar titled, Reducing Design Cost and Time With Concurrent DFM Verification. The webcast will take place Jun 2, 2010 from 2:00 PM to 2:45 PM (Eastern US time). The online seminar is ideal for CAD management with time and cost objectives, NPI engineers seeking to achieve first pass manufacturability, and PCB designers trying to efficiently integrate manufacturing constraints into their design process. The webinar will be presented by Patrick McGoff of Mentor Graphics.
Mentor Graphics introduced the Calibre InRoute design and verification platform. Calibre InRoute enables engineers to natively invoke Calibre tools within the Olympus-SoC place and route system to achieve true manufacturing closure during physical design. The Calibre InRoute automatically detects and fixes DRC violations and performs design for manufacturing (DFM) enhancements while optimizing for area, timing, power and signal integrity.
The 2010 SEMATECH Knowledge Series (SKS) conferences will focus on difficult questions in lithography, advanced technologies, manufacturing, and strategy. Included are a new set of meetings on installed-base equipment utilization, and a new interconnect workshop in stress management for 3D chips utilizing through-silicon vias (TSVs). All SKS meetings are open to the public.