Tag Archives: Low power

Microchip XLP 16-bit Energy Harvesting Development Kit

Microchip Technology and Cymbet teamed to create the customizable XLP 16-bit Energy Harvesting Development Kit. The energy harvesting kit includes a modular development board with the PIC24F16KA102 microcontroller. The included Cymbet EnerChip EH Eval-08 Energy Harvesting Board harvests solar energy that is then stored in the EnerChip solid-state, rechargeable energy-storage devices. PICtail daughter boards can be added for the rapid evaluation of a wide variety of system functions, including ZigBee and proprietary wireless connectivity, and SD memory cards. The XLP 16-bit Energy Harvesting Kit (part # DV164133) is available today for $195.

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Magma, Virage Logic Reference Flow for GLOBAL FOUNDRIES 65nm Process

Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.

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2010 International Symposium on Quality Electronic Design

The 2010 International Symposium on Quality Electronic Design (ISQED2010) conference will feature nine multiple interactive tutorials covering challenging design issues. ISQED2010 features 7 keynote speeches by industry leaders, 23 technical sessions with nearly 150 papers in three parallel tracks, panel discussions and vendor exhibits. The conference will take place March 22-24, 2010, at the Doubletree Hotel, San Jose, Calif.

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SMIC-Cadence 65nm Low Power Reference Flow 4.0

Cadence Design Systems introduced a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation (SMIC). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform. The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with an advanced, automated low-power design capability.

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