Mentor Graphics introduced a comprehensive IP to System, UPF-based low-power verification flow. Mentor now has platform-level support of Unified Power Format in both the Questa functional verification platform and the Veloce family of hardware emulators that lets users create a single specification for power intent that is reusable and consistent, and facilitates low-power verification across simulation, formal and emulation.
Avnet Electronics Marketing, Freescale, Murata and ARM are teaming together to host a series of SpeedWay technical seminars. The development board transforms the Freescale Freedom development platform into a completely portable wireless sensor system. The SpeedWay events will discuss ways to incorporate the Wi-Go wireless accessory module with the Freescale Freedom development platform featuring the Kinetis-L microcontrollers. The workshops feature both in-person presentations and hands-on labs.
Cadence Design Systems is holding a Low-Power Technology Summit. The event will be keynoted by UC Berkeley Professor Jan M. Rabaey. He is the author of Low Power Design Essentials (Integrated Circuits and Systems). Rabaey will address power issues that impact today’s chip designers. The one-day technical conference will take place on October 18th at Cadence Design Systems in San Jose, California. The event is free.
Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.
Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.
Apache Design Solutions is offering a series of low-power webinars. The webcasts will cover low power methodologies, IP integration, chip-package-system solutions, RTL power analysis, SoC power integrity, analog mixed-signal power noise, full-chip ESD integrity, and IC package power. The eight online seminars will take place at 11am (PDT) in the months of July and August.
Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.
Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s 32/28-nm process technology.
The Silicon Integration Initiative (Si2) will hold their annual OpenAccess+ Conference on October 20, 2010 in Santa Clara, CA. The Si2 OpenAccess+ Conference will cover the inter-related areas of OpenAccess, Design for Manufacturability (DFM), Low Power design and the newest Coalition for Open PDKs. The event will include a DFM session on the OpenDFM meta language standard, which describes DRC and DFM checks in a tool-agnostic fashion. The conference will provide updates on the industry adoption of OpenAccess and plans for the future for all coalitions.