Tag Archives: logic

ProPlus Design Solutions Debuts NanoYield Design for Yield Software

ProPlus Design Solutions launched NanoYield design for yield software. It is a fast and accurate yield prediction and optimization tool for memory, logic, analog and digital circuit design. The toolset is faster than traditional Monte Carlo analysis for both regular three-sigma and advanced six-sigma analysis. NanoYield is part of ProPlus Design Solutions’ transistor-level statistical modeling and design and variations-aware product portfolio. It is shipping now.

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Gates-on-the-Fly Fixes Logic Equivalence Check Failures White Paper

SynaptiCAD recently published a white paper that describes how their updated Gates-on-the-Fly (GOF) was used to find and fix failures identified by Cadence’s Conformal tool. SynaptiCAD’s Verilog netlist editor was updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. Gates-on-the-Fly graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool.

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Logic AM1808 System on Module and Development Kits

Logic announced the AM1808 System on Module (SOM) and the Zoom AM1808 Development Kits for the Texas Instruments Incorporated (TI) AM1808 microprocessor. The Logic AM1808 SOM and development kits can accelerate product development of embedded systems by four to six months. Logic’s AM1808 SOM-M1 and Zoom AM1808 Development Kits are available now. The suggested retail price for the EVM Development Kit is $1,150 and for the eXperimenter Kit is $445.

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SEMATECH to Reveal Device and Process Breakthroughs at IEDM

At the IEEE International Electron Devices Meeting (IEDM), engineers from SEMATECH’s Front End Processes (FEP) program will present technical papers revealing research breakthroughs. SEMATECH experts will report on low defect density high-k gate stacks for alternative III-V channel materials and non-planar devices, and discuss a new dry etch approach to minimize etch related leakage — a significant process technology advancement for next-generation logic and memory technologies. The IEDM Conference will take place December 7-9, 2009, at the Hilton in Baltimore, MD.

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