Tag Archives: lithography

Micro- and Nanopatterning of Inorganic and Polymeric Substrates by Indentation Lithography

The Whitesides Group at Harvard University and CSM Instruments published an nanotech article on complex 3D-nano patterns with Indentation Lithography (IndL) and piezo technology. The paper describes the use of a nanoindenter, equipped with a diamond tip, to form patterns of indentations on planar substrates (epoxy, silicon, and SiO2). The indentations have the form of pits and furrows, whose cross-sectional profiles are determined by the shapes of the diamond indenters, and whose dimensions are determined by the applied load and hardness of the substrate.

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Magma Excalibur-Litho Fab Analysis Framework for Lithography

Magma Design Automation introduced Excalibur-Litho fab analysis framework for the development and monitoring of advanced lithography solutions. The tool collects and organizes design and real-time data from the semiconductor manufacturing floor (such as defectivity, metrology and tool history). Excalibur-Litho is built on an open-architecture database that enables safe and secured CAD access and easy fab integration.

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Synopsys Proteus LRC for Lithography Verification

Synopsys announced Proteus LRC (lithography rule check) for lithography verification. Proteus LRC is a post-optical proximity correction (OPC) verification tool. It enables fast and accurate hotspot detection across the process window for full-chip mask validation within the highly-scalable Proteus Pipeline Technology. Synopsys Proteus LRC is designed for 28-nanometer (nm) and below. It features OPC models and rigorous first-principle models from embedded Sentaurus Lithography technology. Proteus LRC is integrated into the Proteus Mask Synthesis flow.

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KLA-Tencor PROLITH X3.1 Virtual Lithography Tool

PROLITH X3.1, from KLA-Tencor, is a comprehensive toolset that addresses advanced lithography challenges. PROLITH X3.1 virtual lithography tool helps researchers quickly and cost-effectively troubleshoot challenging issues in EUV and double patterning lithography (DPL) processes, including line edge roughness (LER) and patterning issues associated with wafer topography. With PROLITH X3.1, lithographers can streamline research, conserve valuable lithography cell resources, and accelerate product development.

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SEMATECH and ISMI Presentations at SPIE Advanced Lithography 2010

At SPIE Advanced Lithography 2010, SEMATECH will discuss issues and solutions in preparing extreme ultraviolet lithography (EUVL) for high-volume manufacturing. The SPIE Advanced Lithography conference will take place February 21-25 in San Jose, CA. SEMATECH will show how they are enabling EUV mask and resist/materials infrastructure as well as EUVL manufacturing feasibility and affordability. The SEMATECH Lithography Program is based at the College of Nanoscale Science and Engineering’s (CNSE) Albany NanoTech Complex.

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SEMATECH Knowledge Series Conferences 2010

The 2010 SEMATECH Knowledge Series (SKS) conferences will focus on difficult questions in lithography, advanced technologies, manufacturing, and strategy. Included are a new set of meetings on installed-base equipment utilization, and a new interconnect workshop in stress management for 3D chips utilizing through-silicon vias (TSVs). All SKS meetings are open to the public.

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