Aldec introduced ALINT 2010.06, which is a design rule checking software solution. ALINT 2010.06 features a phase-based linting (PBL) methodology that provides structured and prioritized phases for the analysis of HDL design issues. The design rule checking tool reduces the number of linting iterations and error messages at each phase. ALINT eliminates more design issues incrementally at each phase. Default phases may be modified or customized by engineers for adherence to corporate design policies or conducting targeted design rule checks. The latest release of ALINT is available now. The tool supports STARC, RMM, DO-254 and Aldec design rule plug-ins, which are sold separately.
Real Intent rolled out version 1.3 of Ascent Lint. The new version adds VHDL checks to its existing Verilog checks. It is a tool that performs syntax and semantic Hardware Description Language (HDL) lint checks for complex SoC designs. Ascent Lint features a fast engine and low noise report for debugging electronic designs. Ascent Lint 1.3 is available now.
Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.