Tag Archives: Library

CoWare ARM Model Library Supports Cortex-A5, Cortex-M4 Processors

CoWare’s SystemC-based software development solution now supports Fast Models from ARM for Cortex-A5 and Cortex-M4 processor IP. The CoWare software development solutions already include support for Fast Models from ARM for the Cortex-A9, Cortex-A8, Cortex-R4 and Cortex-M3 processors. The ARM Cortex IA Model Integration Library to enable usage of Cortex-A5, Cortex-A8, Cortex-A9, Cortex-R4, Cortex M3 and Cortex-M4 Fast Models from ARM in CoWare Virtual Platform and CoWare Platform Architect is available from CoWare now.

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Imec and Altos Team on Chip Design and Prototyping Service

Imec and Altos Design Automation will to set up a library re-characterization service based on Altos characterization tools. imec will extend their ASIC (application-specific integrated circuit) prototyping and volume fabrication service with library re-characterization, which is essential when designing in 65nm and 40nm nodes.

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Nangate 45nm Open Cell MegaLibrary

Nangate has released the 45nm Open Cell MegaLibrary. It supports the existing 45nm Open Cell Library that has become a standard for university research programs and in EDA and fabless organizations since it was first released in 2008. The 45nm Open Cell MegaLibrary helps designers explore extra design performance gains before implementing with a foundry specific MegaLibrary on their production process node.

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Bluespec Pipelined Architecture Composers Library

The Bluespec Pipelined Architecture Composers library (PAClib) is a parameterized, plug-and-play building block library for specifying, modeling, and synthesizing algorithm and datapath designs. PAClib is available in source-code form, making it fully extensible and modifiable for developers. PAClib consists of a set of standard pipeline building blocks, user parameterized by computational functions, structures, buffering and data types.

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Aldec ALINT 2009.10 for Design Rule Checking

Aldec introduced ALINT 2009.10 Design Rule Checking application. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT is Design Rule Checking software for fast design closure. ALINT analyzes and detects issues early in the design and verification cycle, and checks HDL source code of complex ASIC, FPGA, and SOC designs. It detects such problems as poor coding styles, improper clock and reset management, simulation and synthesis problems, poor testability, and source code issues throughout the design flow.

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CoWare SBL-301 SystemC Bus Library for Platform Architect and AMBA

The CoWare SBL-301 SystemC Bus Library for Platform Architect enables early configuration, exploration, and optimization of next-generation system-on-chip (SoC) architectures using AMBA technology-based virtual platforms in SystemC. The new CoWare SBL-301 SystemC Bus Library and architecture design solution featuring CoWare Platform Architect and AMBA designer ADR-301 is available for early customer evaluation now. Production release is expected in December 2009.

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