Tag Archives: Layout

Cadence Debuts Allegro v16.6 Package Designer and SiP Layout Solution

Cadence Design Systems Allegro v16.6 Package Designer and System-in-Package (SiP) Layout solution

Cadence Design Systems released version 16.6 of their Allegro Package Designer and System-in-Package (SiP) Layout solution. Allegro now enables engineers to analyze and validate high-performance, low-power devices for electrical compliance. This improves design time and speeds time to market. New enhancements in Cadence Allegro enable a more predictable and efficient design cycle. Cadence Allegro release 16.6 IC package solution is expected to be available in the fourth quarter of this year.

Continue reading

AWR Connected for ODB++

AWR Connected for ODB++ is a PCB layout verification design flow for connecting third party PCB tools and AWR software (Microwave Office RF/microwave circuit simulation and AXIEM electromagnetic analysis software). It enables the flow of PCB layout data (exported from vendor tools in ODB++ format) into AWR’s Microwave Office / AXIEM software for post-layout, final design-stage verification. The ODB++ PCB flow moves layout data from an engineer’s PCB vendor tool into a relevant and independent file format ready for use and import into AWR software. AWR Connected for ODB++ is available now.

Continue reading

Gates-on-the-Fly Fixes Logic Equivalence Check Failures White Paper

SynaptiCAD recently published a white paper that describes how their updated Gates-on-the-Fly (GOF) was used to find and fix failures identified by Cadence’s Conformal tool. SynaptiCAD’s Verilog netlist editor was updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. Gates-on-the-Fly graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool.

Continue reading

Synopsys Design Compiler 2010

Synopsys introduced Design Compiler 2010. The tool enables RTL designers to perform floorplan exploration within the synthesis environment to efficiently achieve an optimal floorplan. Design Compiler’s new scalable infrastructure tuned for multicore processors results in 2X faster synthesis runtimes on four cores. Design Compiler 2010 reduces iterations and run times in physical implementation.

Continue reading

Synopsys Galaxy Custom Designer with SmartDRD Technology

Synopsys Galaxy Custom Designer now features SmartDRD design-rules-driven technology. SmartDRD technology enables layout engineers to more quickly achieve design-rule-check (DRC) clean designs with significantly reduced effort for analog and custom designs. SmartDRD automates many DRC repair tasks. Until now, custom layout has been primarily handled using manual methods. With SmartDRD technology, layout engineers can identify and fix DRC violations in just seconds.

Continue reading