Tag Archives: Keynote

Low-Power Technology Summit Features Jan M. Rabaey

Cadence Design Systems is holding a Low-Power Technology Summit. The event will be keynoted by UC Berkeley Professor Jan M. Rabaey. He is the author of Low Power Design Essentials (Integrated Circuits and Systems). Rabaey will address power issues that impact today’s chip designers. The one-day technical conference will take place on October 18th at Cadence Design Systems in San Jose, California. The event is free.

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DVCon 2012 Features Tutorials, Panels, Technical Sessions, and Keynote

This year’s Design and Verification Conference and Exhibition will take place next week, February 27th to March 1st, in San Jose, California. DVCon 2012 is a conference for functional design and verification. The event will focus on bringing information from the leading edge of technology, techniques, standards and methods. This year’s DVCon Expo will feature tutorials, panels, technical sessions and 34 exhibitors.

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2011 Common Platform Technology Forum

The 2011 Common Platform Technology Forum will take place at the Santa Clara Convention Center on January 18th. The forum will present technical details of the 28nm HKMG design for low-power applications. The event will also include technology advancements in SoC enablement solutions, materials science, process technology and manufacturing. The Common Platform alliance was formed by IBM, Samsung Electronics and GLOBALFOUNDRIES. The alliance focuses on jointly developed digital CMOS process technologies and advanced manufacturing.

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