Tag Archives: JTAG Embedded Testing

Corelis Runner-Lite JTAG Test Executive

Corelis introduced Runner-Lite, which is a free software test executive for performing boundary-scan testing, JTAG Embedded Testing (JET), and in-system device programming using pre-generated test plan files built for specific reference boards. Runner-Lite features unrestricted access to complete off-the-shelf JTAG structural and functional test solutions for many silicon vendor reference designs. The tool enables engineers to familiarize themselves with Corelis test capabilities and can be use as a test bench for reference board based designs.

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