Synopsys announced DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP includes few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. DesignWare AEON embedded NVM IP is also available for 65nm to 250nm process technologies. DesignWare AEON NVM IP is ideal for wireless, RFID and analog and mixed-signal SoC designs.
According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI Express 3.0 is available now.
Carbon Design Systems announced a TLM-2.0 solution for the AMBA protocol. The solution enables modeling the AMBA protocols with SystemC TLM2-0. The TLM-2.0 for the AMBA protocol solution will execute in any SystemC environment and contains no runtime licensing. Engineers can create models representing AMBA intellectual property (IP) blocks at any level of abstraction. The TLM-2.0 for the AMBA protocol solution is available for free from Carbon’s IP Exchange.
Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.
Synopsys introduced their new DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP. The Sonic Focus Stereo IPs enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The new Sonic Focus Stereo IP solutions are ideal for low-power DSP and cost-effective embedded stereo audio applications. The Synopsys DesignWare Sonic Focus Stereo IP solutions are available now.
Synopsys’ DesignWare STAR Memory System product family now features Self-Test and Repair Error Correcting Codes. The DesignWare STAR ECC IP is a configurable IP solution that enables designers to achieve a higher level of protection against transient errors compared to the classic ECC approach and deliver a more reliable product to the market. The DesignWare STAR ECC IP is designed to provide optimal performance of partial word writes and improved error detection/correction capability in multi-bit upsets and random bit errors.
Synopsys will host an online synposium from August 31st to September 2nd. The virtual event will feature Synopsys’ EDA software, IP, prototyping, and services for semiconductor design, verification and manufacturing. During the event, engineers can chat with Synopsys technical staff and view product demos, webinars, and technical papers. Designers can view synposium materials on-demand through December 3, 2010.
Innovasic Semiconductor’s RapID Platform is a EtherNet/IP connectivity solution. Engineers can download the entire platform for a risk-free, no cost evaluation. A one-time license fee applies only if the platform is used in production. Evaluation of the RapID Platform download can be performed on hardware via the Internet or at the user’s site.
Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.
Atrenta launched SpyGlass-Physical tool for early implementation analysis. SpyGlass-Physical provides early estimates of area, power, timing and routability for RTL designers without the need for physical design expertise or tools. The tool helps to achieve performance targets in concurrent block/SoC development processes by using interactive implementation analysis features. The result is enhanced guidance for the actual implementation of both IPs and full-chip SoCs. SpyGlass-Physical is currently in limited deployment.