Tag Archives: IP

Forte Design Systems Launches New Version of Cynthesizer SystemC High-level Synthesis

Cynthesizer SystemC high-level synthesis (HLS) ~ Forte Design Systems

Forte Design Systems launched a new version of Cynthesizer SystemC high-level synthesis (HLS). Cynthesizer v4.3 features improvements in power results and ease of use while expanding their CynWare IP library. This enables design teams to quickly adopt high-level synthesis. New features include new modeling style support, expanded optimization and analysis capabilities, integration with third-party tools and improvements to CynWare intellectual property (IP) cores. Version 4.3 of Forte Cynthesizer is shipping now.

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Cadence Incisive Debug Analyzer Reduces Debug Time by 40%

Cadence Design Systems launched the Incisive Debug Analyzer. The new tool is a verification debug solution for RTL, testbench and SoC verification. It helps designers reduce debug time and effort. The Incisive Debug Analyzer integrates seamlessly into existing Incisive debug flows, fully leveraging SimVision for waveform and transaction-level debug. The tool will be released at the end of the year.

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Cadence PCI Express Verification IP Supports PCIe PIPE4 Specification

Cadence Design Systems has added new capabilities in their PCI Express Verification IP. The Cadence PCIe VIP now offers more in-depth verification of the most current PCI Express specification at both the block and system-on-chip (SoC) levels. The Cadence PCIe VIP is a broad, highly differentiated, and proven solution with distinct advantages for PCI Express verification. Cadence’s VIP solution includes over 40 interface protocols and more than 6,000 memory models that have been deployed in thousands of designs.

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Synopsys DesignWare IP Available for SMIC 40-nanometer Low-Leakage Process

Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

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Carbon Design Systems and Cadence Design Systems Team on Performance Analysis Kit

Carbon Design Systems and Cadence Design Systems announced the availability of a Carbon Performance Analysis Kit. The CPAK accelerates the intellectual property (IP) benchmark process. The Carbon/Cadence CPAK is available now from Carbon’s IP Exchange web portal. Ported CoreMark benchmarking software is available from coremark.org.

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Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing

Cadence TripleCheck IP Validator for Faster IP Compliance Testing

Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.

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Xilinx Vivado Design Suite Supports All Programmable Devices

Xilinx Vivado Design Suite

Xilinx introduced their Vivado Design Suite, which is an IP and system-centric design environment for accelerating the design of all programmable devices. The Vivado Design Suite version 2012.1 is available as part of an early access program. Public access will start with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 extensible processing platform (EPP) support later in the year. ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost.

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New Cadence Book: Advanced Verification Topics

Cadence Design Systems published a new book: Advanced Verification Topics. The 229-page book describes the latest techniques and methodologies for verifying today’s most complex IP and systems on chips (SoCs). It discusses topics like metric-driven verification of digital and mixed-signal designs, low-power verification using the UVM, multi-language UVM, and acceleration for the UVM. The Cadence book is ideal for aid verification engineers. It builds on a prior Cadence book, A Practical Guide to Adopting the Universal Verification Methodology (UVM).

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Cadence Memory Controller and PHY IP Supports ONFI 3

Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. The Cadence ONFI 3 memory controller and PHY IP are available now. The EDA company is also offering supporting verification IP (VIP) and memory models to ensure successful implementation.

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IPextreme Xena Platform for Semiconductor IP Operations

IPextreme launched Xena, which is a complete, secure, scalable platform for managing semiconductor IP. There are two product offerings: Xena Cloud and Xena Enterprise. With the enterprise version, companies host Xena on their own internal servers, handle administration of the server, and have unlimited numbers of users. With the cloud version, Xena is hosted in the cloud with IPextreme handling the administration of the host server. The company buys subscriptions for its Xena users. In both models, customers of IP providers can use Xena for free.

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