Tag Archives: IP Validator

Cadence TripleCheck IP Validator Simplifies and Automates IP Compliance Testing

Cadence TripleCheck IP Validator for Faster IP Compliance Testing

Cadence Design Systems introduced their TripleCheck IP Validator. The test suite supports all major logic simulators, and it provides a simulator-independent native SystemVerilog and/or e coverage database that supports both leading test bench languages. Cadence TripleCheck IP Validator is available now for PCIe Gen 3. Cadence has support for several additional protocols in development for release later this year.

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