Cadence Design Systems introduced the Secure Digital (SD) 4.0 Host Controller Intellectual Property core. The IP core helps designers achieve the maximum memory card access performance of up to 312MB/s (three times the performance of the previous specification). The Secure Digital 4.0 Host Controller IP core is available now.
Tensilica announced their imaging and video dataplane processor. The IVP DSP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing. The IP core supports increasing sensor resolutions. The IVP DPU is available for broad licensing now. The core is ideal for the complex image/video signal processing functions in mobile handsets, tablets, digital televisions (DTV), automotive, video games and computer vision based applications.
Tensilica announced their HiFi Mini DSP IP core. According to the company, the digital signal processor core is the smallest, lowest power DSP IP core supporting always listening voice trigger and speech command modes. The HiFi Mini DSP IP core will be available in March 2013. The core is ideal for smartphones, tablets, appliances, and automotive applications.
Cortus announced their APS5 embedded microcontroller. The Cortus APS5 is a 32-bit general purpose CPU. The processor IP is designed for demanding embedded systems. It features a high performance integer unit and an instruction cache. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.
Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.
Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement of over 150% for most voice codecs compared to HiFi EP. The HiFi 3 has been delivered to lead customers. General availability will be in March.
The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of over 1 GHz in 45 nm process technology (45GS) with an area of just 0.044 mm2. The configurable and extensible Xtensa LX4 DPU is available now. The IP core is ideal for handling complex compute-intensive DSP applications where an RTL implementation may be the only other option.
Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.
Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not encumbered by patents, and has an open-source reference implementation. Tensilica’s FLAC decoder supports both stereo and multi-channel formats.
The Evatronix C65C02 IP core is a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology. The C65C02 is a fast 8-bit microprocessor IP that implements the same instruction set as the 65C02 microprocessor chip, which is an upgraded version of the NMOS-based MOS Technology 6502 8-bit CPU. The Evatronix C65C02 IP core is available for licensing now. The core includes synthesis and simulation support scripts for most environments, Verilog or VHDL test bench, and a reference design for the proprietary evaluation board.