Tag Archives: interface

Synopsys DesignWare IP Available for SMIC 40-nanometer Low-Leakage Process

Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

Continue reading

Introducing QTouch Studio 4.0 Webinar

Atmel will host a webinar titled, Free & Easy: Introducing QTouch Studio 4.0. The webcast will demonstrate how to design touch interfaces with Atmel’s QTouch Studio 4.0 and Altium Designer 4.0. The free one-hour seminar will take place Thursday, March 25, 2010 at 12 pm ET / 9 am PT. The QTouch Studio webinar will be presented by Steve Berry (director of touch marketing) and Arild Rodland (product marketing manager).

Continue reading

Jasper Design Automation Formal Verification Proof Kits

Jasper Design Automation rolled out Proof Kits for LPDDR1 and LPDDR2, and DDR3 SDRAM. The new LPDDR and DDR3 Proof Kits both speed verification for these high-demand memories, and ensure conformance with industry standards. The new DDR Proof Kits are currently available as a chapter within Jasper Formal Testplanner, and provided at no additional charge to current licensees of Formal Testplanner.

Continue reading