Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.
Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.
Jasper Design Automation announced Intelligent Proof Kits for accelerated certification of advanced SoC interconnect protocols. Jasper Intelligent Proof Kits ship unencrypted with original source code to facilitate user customization and insights into the protocols themselves. Jasper is initially releasing Intelligent Proof Kits for AMBA 3 and AMBA 4. DFI, DDR and LPDDR versions will roll out a little later.
The PCI Express Base 3.0 specification is now available to PCI-SIG members. The PCI Express Base 3.0 specification describes the PCI Express architecture, interconnect attributes, fabric management, and the programming interface required to design and build systems and peripherals that are compliant with the PCI Express Specification. PCIe 3.0 technology maintains backward compatibility with previous PCIe architectures and is ideal for high-volume platform I/O implementations across a wide range of topologies (servers, workstations, desktop and mobile personal computers, embedded systems, peripheral devices, etc).
The 2010 SEMATECH Knowledge Series (SKS) conferences will focus on difficult questions in lithography, advanced technologies, manufacturing, and strategy. Included are a new set of meetings on installed-base equipment utilization, and a new interconnect workshop in stress management for 3D chips utilizing through-silicon vias (TSVs). All SKS meetings are open to the public.
The CoWare SBL-301 SystemC Bus Library for Platform Architect enables early configuration, exploration, and optimization of next-generation system-on-chip (SoC) architectures using AMBA technology-based virtual platforms in SystemC. The new CoWare SBL-301 SystemC Bus Library and architecture design solution featuring CoWare Platform Architect and AMBA designer ADR-301 is available for early customer evaluation now. Production release is expected in December 2009.