ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.
Satin IP Technologies will be in a panel at the IP-Embedded Systems Conference in Grenoble, France on December 1, 2009 from 17:15 to 18:45. They will discuss improving intellectual property (IP) quality without losing design productivity. The panel (entitled Improving IP Quality vs. Losing Design Productivity – What Are the Tradeoffs?) will discuss issues that arise when time-to-market and cost reductions dominate IP design and integration, since instituting design practices for enhanced quality can be seen as overhead by engineers and engineering managers.
Cypress Semiconductor rolled out over 30 intellectual property (IP) elements for the new PSoC 3 programmable system-on-chip architectures. The embedded design resources include example projects, application notes, and solution overviews. The resources enable engineers to quickly implement designs using the unique new PSoC Creator integrated development environment (IDE). The solution IP Elements are available for free online.