Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.
Synopsys introduced IC Compiler-Advanced Geometry, which is a new configuration of their IC Compiler physical design product. IC Compiler-Advanced Geometry is a DPT-compliant place-and-route solution that will provide designers moving to 20 nanometers with an advanced solution. Synopsys has successfully collaborated with foundry partners and major customers to validate that IC Compiler is 20nm-ready.