Tag Archives: Implied Intent Verification

Real Intent Updates Ascent Implied Intent Verification, X-Verification

Real Intent Ascent Implied Intent Verification (IIV)

Real Intent launched the latest version of Ascent Implied Intent Verification (IIV) and Ascent X-Verification (XV) tools. Ascent IIV and Ascent XV offer enhanced support for SystemVerilog, Verilog and VHDL languages, and improve ease of use in both the GUI and low-noise reporting of design issues. The tools also include Verdi3 integration. The newest releases of Ascent IIV and Ascent XV are available now for download. The EDA tools are ideal for early functional analysis of digital designs.

Continue reading