Tag Archives: IEEE-ISTO

Synopsys Develops Doubles Patterning Technology Model Extensions

Synopsys recently worked with the members of the Interconnect Modeling Technical Advisory Board (IMTAB) of the IEEE Industry Standards and Technology Organization (IEEE-ISTO). The collaboration has resulted in a parasitic variation modeling solution to address the effects of double patterning technology (DPT), targeted for use in 20-nanometer (nm) IC manufacturing.

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