Tag Archives: HiPer Simulation AFS

Tanner HiPer Silicon v15.23 Features HiPer Simulation AFS and T-AFS

Tanner EDA's S-Edit design environment for schematic capture

Tanner EDA introduced the latest version of HiPer Silicon full-flow analog and mixed-signal design suite. HiPer Silicon v15.23 includes HiPer Simulation AFS and Tanner Analog FastSPICE (T-AFS), which integrates the Berkeley Design Automation Analog FastSPICE Platform with Tanner EDA’s S-Edit schematic capture and W-Edit waveform analyzer.

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