Tanner EDA announced a seminar for next week. The title of the event is Driving Innovation in Image Sensors and High Speed Analog/Mixed-Signal Design. The Lunch & Learn seminar will be moderated by SemiWiki founder Dan Nenni and will discuss the challenges and opportunities for improving productivity in analog and mixed-signal (A/MS) IC design. The seminar will take place on Thursday, October 24th, at TechMart in Santa Clara, California.
Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.
Cadence Design Systems launched version 16.6 of their Allegro printed circuit board technology. The PCB tool is the first electrical CAD (ECAD) team collaboration environment for PCB design using Microsoft SharePoint technology. Cadence Allegro, integrated with SharePoint, improves team collaboration, design creation and control, and significant productivity improvements. Allegro v16.6 will be available in the fourth quarter of this year.
Corelis announced their usPro-S high-speed multi-IO SPI host adapter. The BusPro-S is a USB-powered desktop instrument that helps engineers reduce development time. The Corelis tool provides low level control of Serial Peripheral Interface (SPI) buses for the generation of SPI messages and programming SPI memory. The BusPro-S comes complete with hardware, software, and cables. The tool will be available soon with an introductory list price of $675.
Analog Devices will host a free webinar about the JESD204B standard. The online seminar will take place Wednesday, April 18, 2012 at 12:00 pm EDT. The title of the webcast is Demystifying the JESD204B High-speed Data Converter-to-FPGA Interface. The ADI webcast is ideal for engineers designing within the FPGA/analog signal chain system ecosystem.
Sigrity announce a series of seminars. The free multi-city seminars will discuss high-speed design challenges associated with power integrity, signal integrity, and EMI issues. The seminar series will address issues associated with simultaneous switching output (SSO) and assessing end-to-end high-speed serial links. The Sigrity seminars will take place in Boston, Austin, Dallas and Dana Point (southern California) on November 15, 16, 17 and 18, respectively. The events are ideal for designers involved in projects at the chip, package and system level interested in solutions for high-speed power integrity, signal integrity and EMI issues.
NXP Semiconductors has an archived webinar about maintaining signal integrity when placing ESD devices on high speed differential signals. Topics covered in the webcast include: Capacitance, inductance, and methods of impedance matching, maintaining eye openings, and minimizing jitter and skew. During the online seminar, NXP will compare signal integrity challenges with different ESD solutions.
NXP Semiconductors is offering a webinar, ESD Design for High Speed Interfaces: Critical Design Considerations, on Tuesday, December 8, 2009 11:00 am EST (8:00 am PST, 16:00 GMT). In the webcast, you will learn about design consideration for choosing ESD protection devices for high speed interface protection. The online seminar will cover comparisons of performance, other available solutions, layout techniques for improving overall performance, and recent advances in protection architectures.