Tag Archives: HDL

SynaptiCAD Introduces SimSwapper Simulator Swapper Tool

SynaptiCAD SimSwapper simulator swapper and command line options translator tool

SynaptiCAD introduced SimSwapper, which is a simulator swapper and command line options translator tool. The EDA tool enables engineers to re-use simulation regression scripts with simulators from multiple EDA vendors. SimSwapper reduces the burden of swapping between simulators from different EDA vendors. A one-year license for SimSwapper with SystemVerilog support is regularly priced at $500. However, for a limited time, the tool can be purchased for a promotional price of $350. SimSwapper is available on Windows and Linux platforms.

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Updated SynaptiCAD BugHunter Supports C++ and SystemC

The SynaptiCAD BugHunter graphical test bench generator and HDL debugger now supports SystemC and C++. Standalone SystemC and mixed SystemC/Verilog/VHDL simulations can be compiled and debugged under the BugHunter GUI. A node-locked license for BugHunter sells for $2500 on Windows. Floating licenses sell for $5000 on Windows and $6000 on Unix.

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Aldec ALINT 2009.10 for Design Rule Checking

Aldec introduced ALINT 2009.10 Design Rule Checking application. The product includes “best-practice” design rules for fast design closure of safety critical DO-254/ED-80 Avionics designs. ALINT is Design Rule Checking software for fast design closure. ALINT analyzes and detects issues early in the design and verification cycle, and checks HDL source code of complex ASIC, FPGA, and SOC designs. It detects such problems as poor coding styles, improper clock and reset management, simulation and synthesis problems, poor testability, and source code issues throughout the design flow.

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