Tag Archives: GLOBALFOUNDRIES

Cadence and GLOBALFOUNDRIES In-Design DRC+ Verification Flow

Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

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2011 Common Platform Technology Forum

The 2011 Common Platform Technology Forum will take place at the Santa Clara Convention Center on January 18th. The forum will present technical details of the 28nm HKMG design for low-power applications. The event will also include technology advancements in SoC enablement solutions, materials science, process technology and manufacturing. The Common Platform alliance was formed by IBM, Samsung Electronics and GLOBALFOUNDRIES. The alliance focuses on jointly developed digital CMOS process technologies and advanced manufacturing.

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Magma, Virage Logic Reference Flow for GLOBAL FOUNDRIES 65nm Process

Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.

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