Tag Archives: Gates-on-the-Fly

Gates-on-the-Fly Fixes Logic Equivalence Check Failures White Paper

SynaptiCAD recently published a white paper that describes how their updated Gates-on-the-Fly (GOF) was used to find and fix failures identified by Cadence’s Conformal tool. SynaptiCAD’s Verilog netlist editor was updated to support easy correction of logic equivalence failures introduced during modifications to post-synthesis netlists, using equivalence check reports from either Cadence’s Conformal LEC or Synopsys’s Formality. Gates-on-the-Fly graphically analyzes and edits large Verilog netlists that have been generated from a synthesis or layout tool.

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SynaptiCAD EDA Tool Suite, Version 15

SynaptiCAD EDA Tool Suite, version 15, features new versions of WaveViewer, Timing Diagrammer, WaveFormer, DataSheet, VeriLogger Extreme, BugHunter, TestBencher Pro and V2V. SynaptiCAD EDA Tool Suite v15 also includes improvements to the Gates-On-The-Fly Netlist Editor.

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Gates-on-the-Fly Netlist Editor with Waveform Viewer Interoperability

SynaptiCAD’s Gates-on-the-Fly (GOF) Verilog netlist editor and incremental schematic viewer now features schematic back annotation and waveform viewer cross-probing. Using one of SynaptiCAD’s waveform viewers, designers can view waveforms from a simulation (e.g. a VCD file) or a logic analyzer and show specific logic states annotated on GOF schematic windows. The schematic and the waveform displays are linked so that engineers can quickly control the simulation time that is displayed from either the schematic or the waveform windows.

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