Tag Archives: Gate-level Simulator

Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog verification capabilities. Riviera-PRO 2010.06 verification platform is available now.

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