Real Intent launched the latest version of Ascent Implied Intent Verification (IIV) and Ascent X-Verification (XV) tools. Ascent IIV and Ascent XV offer enhanced support for SystemVerilog, Verilog and VHDL languages, and improve ease of use in both the GUI and low-noise reporting of design issues. The tools also include Verdi3 integration. The newest releases of Ascent IIV and Ascent XV are available now for download. The EDA tools are ideal for early functional analysis of digital designs.
Cadence Design Systems released version 12.2 of their Incisive functional verification platform and methodologies. Cadence Incisive v12.2 provides the productivity improvements the engineering teams need to bring their designs to market fast and at high quality. The tool features a broad set of new and enhanced capabilities that double the productivity of SoC verification over the previous version.
According to Mentor Graphics, their Questa and Veloce functional verification platforms have expanded their support for designs based on the latest ARM Cortex processors and AMBA bus interfaces. The Questa Codelink with support for ARM Cortex A7, Cortex A15, other Cortex A-family, Cortex R-family, and Cortex M-family processors and Questa Verification IP with support for AMBA4 ACE are available now.
Mentor Graphics will conduct a technical seminar about the challenges of design and functional verification for complex multi-core SoC designs. The event, Design and Verification in the SoC Era, features keynote sessions delivered by John Goodenough (ARM) and Harry Foster (Mentor Graphics). It will take place on October 18, 2011 in San Jose, California. The Mentor Graphics seminar will run from 9am to 3pm Pacific time.
CoFluent Studio can now be used for the creation and automatic generation of SystemC models and test cases for the Mentor Graphics Questa functional verification platform. The automatic SystemC transaction-level modeling (TLM) code generation allows reuse of IC and use case models for validating the register-transfer level (RTL) implementation in Questa.
Real Intent launched Ascent Lint Version 1.2 for early functional verification. Ascent Lint v1.2 performs syntax and semantic Lint checks for complex SoC designs. Ascent Lint now offers rules from STARC Policy, Verilog and SystemVerilog Gotchas, Reuse Methodology Manual (RMM), Principles of Verifiable RTL Designs, and rules based on Real Intent industry expertise.