Tag Archives: Full-flow

Tanner EDA HiPer Silicon v15.11

Tanner EDA rolled out version 15.11 of HiPer Silicon design suite. HiPer Silicon offers engineers a complete analog design flow from schematic capture, circuit simulation, and waveform probing to physical layout and verification. New features in HiPer Silicon v15.11 includes S-Edit additions, T-Spice performance improvements, W-Edit enhancements, L-Edit productivity gains, HiPer DevGen additions, and HiPer Verify enhancements.

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