Avnet Electronics Marketing Americas announced the CC3000-Pmod Compatible Wi-Fi Adapter. The Pmod compatible CC3000-based Wi-Fi adapter development kit features a built-in internet protocol stack. It is designed to attach to Avnet FPGA development boards and other host boards with a Pmod interface connector. The fully integrated and pre-certified Wi-Fi adapter is priced at $59.
Synopsys introduced an integrated hybrid prototyping solution. The out-of-box solution features Synopsys’ Virtualizer virtual prototyping and Synopsys’ HAPS FPGA-based prototyping. By integrating the strengths of Virtualizer virtual prototyping with HAPS FPGA-based prototyping using the UMRBus physical link, Synopsys enables designers to develop fully operational SoC prototypes much faster and earlier in the design cycle, and accelerate software development and full system validation. The Synopsys hybrid prototyping solution is available now to early adopters.
Analog Devices will host a free webinar about the JESD204B standard. The online seminar will take place Wednesday, April 18, 2012 at 12:00 pm EDT. The title of the webcast is Demystifying the JESD204B High-speed Data Converter-to-FPGA Interface. The ADI webcast is ideal for engineers designing within the FPGA/analog signal chain system ecosystem.
Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.
Cadence Design Systems introduced over 600 new capabilities to improve verification productivity for ASIC and FPGA designers. The capabilities, along with support for the Accellera Universal Verification Methodology (UVM), will expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.
TotalHistory, from GiDEL, is a software only solution that enables engineers to have visibility of any signal in their designs, for virtually unlimited trace depth, with no or minimal degradation in performance. TotalHistory is available with GiDEL’s PROC_SoC ASIC Prototyping Systems and PROC Boards FPGA-based High Performance Computing (HPC) accelerators.
eASIC rolled out eTools 8.1 Design Suite for 45nm Nextreme-2 designs. The eTools 8.1 based design flow helps designers to simply perform front-end design conversion and back-end implementation. New features and enhancements in eTools 8.1 enable designers to reduce overall design time by up to 40% while increasing design performance by up to 30% compared to the previous eTools 8.0 suite. FPGA and ASIC designers can try a 30-day evaluation of eTools 8.1 for free.
Synopsys announced the HAPS-60 series of ASIC rapid prototyping systems for complex SoC design and verification. The HAPS-60 series is an easy-to-use and cost-effective rapid prototyping system that enables early hardware/software co-verification and system-level integration at near-real-time run-rates, using at-speed, real-world interfaces. The HAPS-60 series is built with Xilinx Virtex-6 devices.
Synfora is oferring an on-demand webinar that describes the Fundamentals of ESL Synthesis. The webcast will provide RTL designers, systems engineers, and design managers with technical insight into the benefits of high level synthesis, how it operates, and the kinds of transformations that can be made. The online course is presented by Brian Bailey, who is an independent consultant working in the areas of functional verification and ESL. He provides methodology guidance and technical insights to both the EDA industry and the systems industry.
eASIC introduced eTools 8.0 software suite for implementing 45nm Nextreme-2 designs. The eTools 8.0 tool suite delivers a robust ASIC grade design flow with the simplicity, ease of design, and a cost point that is normally associated with FPGA design tools. By focusing on ease-of-use, and low cost of entry, eASIC is now enabling designers to make a seamless transition to adopting Nextreme-2 devices as a lower cost and lower power alternative to FPGAs and a lower NRE alternative to traditional ASICs.