Tag Archives: Foundry

Cadence and GLOBALFOUNDRIES In-Design DRC+ Verification Flow

Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

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Imec and Altos Team on Chip Design and Prototyping Service

Imec and Altos Design Automation will to set up a library re-characterization service based on Altos characterization tools. imec will extend their ASIC (application-specific integrated circuit) prototyping and volume fabrication service with library re-characterization, which is essential when designing in 65nm and 40nm nodes.

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Nangate 45nm Open Cell MegaLibrary

Nangate has released the 45nm Open Cell MegaLibrary. It supports the existing 45nm Open Cell Library that has become a standard for university research programs and in EDA and fabless organizations since it was first released in 2008. The 45nm Open Cell MegaLibrary helps designers explore extra design performance gains before implementing with a foundry specific MegaLibrary on their production process node.

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X-FAB XO035 Process for Blu-ray and Optical Data Communication

X-FAB Silicon Foundries announced the XO035 0.35 micrometer process. The XO035 foundry process is optimized for Blu-ray and high-speed optical data communication applications. XO035 includes X-FAB’s blue PIN module. The integration of the PIN diode into the 0.35 micrometer CMOS environment enables the design of high-performance photo detectors. The XO035 process is available now.

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Process Design Kits for UMS PH15 and PH25 GaAs MMIC Foundry Processes

AWR and United Monolithic Semiconductors (UMS) introduced enhanced process design kits (PDKs) for the UMS PH15 and PH25 advanced gallium arsenide (GaAs) foundry processes. The enhanced PDKs enable designers to take full advantage of the process capabilities of UMS within AWR’s 2009 Microwave Office design suite including its latest technologies such as iNets, AC0E, AXIEM, and ICED DRC. Engineers can also take advantage of the fact that the PDKs are now release-independent from AWR’s own software upgrade cycle. PDKs from UMS are available to active customers of the UMS foundry and AWR software.

More info: AWR